01 Installing Vivado 02 Vivado Design Flow Part 1 03 Vivado Design Flow Part 2 04 Commonly Asked Question_s from previous Module 05 Fundamentals of Verilog 06 Commonly Asked Question_s from previous Module 07 Modeling Styles 08 Assignment Operators in Verilog 09 FAQ 10 Behavioral Modeling Style 11 Commonly Asked Question_s from previous Module 12 Gate Level Modeling Style 13 Switch level Modeling Style 14 Structural Modeling Style 15 Schematic based Design Entry with IP integrator and Xilinx IP_s 16 Memories 17 Commonly Asked Question_s from previous Module 18 Finite State Machines 19 Commonly Asked Question_s from previous Module 20 Writing Testbenches 21 Hardware Debugging with Vivado (Required Hardware) 22 File IO 23 Projects 24 RTL for Synthesis 25 FPGA Architecture Fundamentals 26 Commonly Asked Question_s from previous Module 27 Interview Preparations 28 Next Step |